
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
LIBRARY lpm;
USE lpm.lpm_components.ALL;

USE WORK.TYPES.ALL;

ENTITY control IS
   PORT( 	
	SIGNAL Opcode 			: IN  STD_LOGIC_VECTOR( 5 DOWNTO 0 );
	SIGNAL RegDst			: OUT STD_LOGIC;
	SIGNAL ALUSrc			: OUT STD_LOGIC;
	SIGNAL MemtoReg			: OUT STD_LOGIC;
	SIGNAL RegWrite			: OUT STD_LOGIC;
	SIGNAL MemRead 			: OUT STD_LOGIC;
	SIGNAL MemWrite			: OUT STD_LOGIC;
	SIGNAL Branch			: OUT STD_LOGIC;
	SIGNAL ALUop			: OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 );
	SIGNAL clock, reset		: IN  STD_LOGIC );
END control;

ARCHITECTURE behavior OF control IS
   
COMPONENT LCELL
	PORT (	a_in	: IN STD_LOGIC; 
   		a_out	: OUT STD_LOGIC);
	END COMPONENT;

	SIGNAL  R_format, Lw, Sw, Beq 	: STD_LOGIC;
	SIGNAL  Opcode_out		: STD_LOGIC_VECTOR( 5 DOWNTO 0 );

BEGIN
	Opcode_out(0) <= Opcode(0);
	Opcode_out(1) <= Opcode(1);
	Opcode_out(2) <= Opcode(2);
	Opcode_out(3) <= Opcode(3);
	Opcode_out(4) <= Opcode(4);
	Opcode_out(5) <= Opcode(5);

	--geracao dos sinais de controle usando os bits de opcode
	R_format		<=  '1'  WHEN  Opcode_out = "000000"  ELSE '0';
	Lw			<=  '1'  WHEN  Opcode_out = "100011"  ELSE '0';
 	Sw			<=  '1'  WHEN  Opcode_out = "101011"  ELSE '0';
 	Beq			<=  '1'  WHEN  Opcode_out = "000100"  ELSE '0';
  	RegDst			<=  R_format;
 	ALUSrc			<=  Lw OR Sw;
	MemtoReg		<=  Lw;
  	RegWrite		<=  R_format OR Lw;
  	MemRead			<=  Lw;
	MemWrite		<=  Sw; 
 	Branch			<=  Beq;
	ALUOp( 1 )		<=  R_format;
	ALUOp( 0 )		<=  Beq; 

END behavior;


